Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has updated its popular linting tool ALINT-PRO to enhance the support of Microchip Technology’s Libero® SoC Design Suite. The new release supports automatic conversion of Libero projects into ALINT-PRO’s environment for static linting and clock domain crossing (CDC) analysis of hardware designs in VHDL, Verilog or SystemVerilog.
Static linting helps detect a wide variety of design issues, including poor coding styles, improper clock and reset management, simulation vs. synthesis mismatches, incorrectly implemented finite state machines (FSM), and other typical source code issues throughout the design flow. CDC analysis is critical to designs with multiple asynchronous clocks and helps mitigate non-deterministic issues such as data incoherence as a result of metastability that inevitably appear in today’s large FPGA and SoC FPGA designs.
“The use of advanced verification tools such as static linting and CDC analysis can significantly reduce the number of non-trivial bugs escaping into production, save engineering resource and more importantly, increase the reliability of FPGA and SoC FPGA designs,” said Louie De Luna, Director of Marketing at Aldec. “We’ve had a long-standing and successful partnership with Microchip FPGA business unit since 1987 and we’re happy to continue our relationship and provide value to their users.”
“FPGA designs are increasing in size and complexity requiring earlier detection of language and structural errors,” said Joe Mallett, Sr. Marketing Manager at Microchip. “Designers using Libero SoC Design Suite can take advantage of Aldec’s ALINT-PRO to help detect functional errors earlier in the FPGA design cycle.”
In conjunction with the latest release of ALINT-PRO, Aldec and Microchip will be conducting a webinar that will be held on March 2, 2023 - Linting and CDC Analysis for Microchip FPGA Designs.
ALINT-PRO 2022.12 is available for download and evaluation.
ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog. It is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, correct FSM descriptions, clock and reset tree issues, CDC, RDC, DFT, and coding for portability and reuse.
Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, High-Performance Computing Platforms, Embedded Development Systems, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.
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